How Verilog Handle Four-Valued Logic

(Uses Verilog): module-endmodule, reg, integer, initial, begin-end,'b, $display, for, ==, ===, != !==, &, ~&, &&, |, ~|, ||, ^, ~^, %b
(REF): Verilog DIGITAL COMPUTER DESIGN: Algorithms into Hardware, by M.G. Arnold; Prentice PTR, 1999 Chapter 3.

In digital circuit we deal primarily with 0's or 1's "strengths" of values but in reality there are four possible values that can be assigned to any signal:

0 - logic LOW
1 - logic HIGH
x - don't care 
z - high Impedance

The Verilog program below when executed in SILOS III will produce how Verilog treat these four values in common Verilog operators consisting of: 

==   - equal to
===  - identical
!=   - not equal
!==  - bitwise not equal
&    - bitwise AND
~&   - bitwise NAND 
&&   - logical AND
|    - bitwise OR
~|   - bitwise NOR  
||   - logical OR
^    - bitwise exclusive OR (XOR)
~^   - bitwise coincidence (XNOR)

Verilog Program, 

//TUT4valued.v
module zx10;
  reg a,b,val[3:0];
  integer ia,ib;

  initial
    begin
      val[0]=1'b0;
      val[1]=1'b1;
      val[2]=1'bx;
      val[3]=1'bz;
      $display
        ("a b  a==b  a===b  a!=a  a!==b  a&b  a~&b  a&&b  a|b a~|b  a||b  a^b  a~^b");

      for (ia=0; ia<=3; ia=ia+1)
        for (ib=0; ib<=3; ib=ib+1)
          begin
            a=val[ia];
            b=val[ib];

            $display
              ("%b %b   %b      %b     %b      %b     %b    %b     %b     %b   %b     %b     %b    %b",
		a,b,a==b,a===b,a!=b,a!==b,a&b,a~&b,a&&b,a|b,a~|b,a||b,a^b,a~^b);
          end
    end
endmodule

Create "New Project",

and click "GO",

SILOS III response, 


                      S I L O S  Version 2001.120    

      DEMO COPY LIMITED TO 200 DEVICES AND 350 LINES OF HDL CODE

       Copyright (c) 2001 by SIMUCAD Inc.   All rights reserved.
       No part of this program may be reproduced,   transmitted,
       transcribed,   or stored in a retrieval system,    in any
       form or by any means without the prior written consent of

         SIMUCAD Inc., 32970 Alvarado-Niles Road, Union City,   
                     California, 94587, U.S.A.                  
                (510)-487-9700  Fax: (510)-487-9721             
          Electronic Mail Address:   "silos@simucad.com"   

!file .sav="TUT4valued"

!control .sav=3

!control .enablecache

!control .savcell=0

!control .disk=1000M

Reading "tut4valued.v"
sim to 0
	Highest level modules (that have been auto-instantiated):
		zx10
	2 total devices.
	Linking ...

	1 nets total: 9 saved and 0 monitored.
	72 registers total: 72 saved.
	Done.                 
a b  a==b  a===b  a!=a  a!==b  a&b  a~&b  a&&b  a|b a~|b  a||b  a^b  a~^b
0 0   1      1     0      0     0    1     0     0   1     0     0    1
0 1   0      0     1      1     0    1     0     1   0     1     1    0
0 x   x      0     x      1     0    1     0     x   x     x     x    x
0 z   x      0     x      1     0    1     0     x   x     x     x    x
1 0   0      0     1      1     0    1     0     1   0     1     1    0
1 1   1      1     0      0     1    0     1     1   0     1     0    1
1 x   x      0     x      1     x    x     x     1   0     1     x    x
1 z   x      0     x      1     x    x     x     1   0     1     x    x
x 0   x      0     x      1     0    1     0     x   x     x     x    x
x 1   x      0     x      1     x    x     x     1   0     1     x    x
x x   x      1     x      0     x    x     x     x   x     x     x    x
x z   x      0     x      1     x    x     x     x   x     x     x    x
z 0   x      0     x      1     0    1     0     x   x     x     x    x
z 1   x      0     x      1     x    x     x     1   0     1     x    x
z x   x      0     x      1     x    x     x     x   x     x     x    x
z z   x      1     x      0     x    x     x     x   x     x     x    x

	0 State changes on observable nets.

	Simulation stopped at the end of time 0.
Ready: