Gate Delays, Static & Dynamic Hazards and Elimination

(Uses Verilog): timescale, module-endmodule, input, output, wire, begin-end, nand, not, reg, #, $monitor, $time, $finish, %b
(REF): Advanced Digital Design with the VERILOG, by M.D. Ciletti, Prentice Hall 2003 Chapter 2.

1. Gate Delays:

Incorporating time delay in digital modeling are easily done in Verilog. If numerical values are desired, then we must introduce Compiler Directive of the form,

'timescale tUNIT / tPRECISION

where: 

tUNIT with values of 1, 10, or 100 followed by time scale unit of s, ms, us, ns, ps, or fs,
tPRECISION gives the resolution of the time scale.
tUNIT must be greater than tPRECISION
In the Verilog Program shown next, the tUNIT=10ns, tPRECISION=1ns, so the inverter not #2(w1,b) means the output w1 which is the invert of input b signal will be available 2 times of the tUNIT later, so 2 x 10ns = 20ns. All the NAND gate has propagation delay of only 10ns each. 

//TUTdelay.v
//Demonstrate delay in circuit: y = a b + /b c 

`timescale 10ns/1ns

module DELAY(y,a,b,c);
  input a,b,c;
  output y;
  wire w1,w2,w3;
  not #2(w1,b);
  nand #1(w2,w1,c);
  nand #1(w3,a,b);
  nand #1(y,w2,w3);
endmodule

//The "Testbench" for DELAY 
module tester;
  reg A,B,C;  //Hold input values
  wire Y;     //Driven output value

//G1 is a Circuit "Instantiation"
  DELAY G1(Y,A,B,C);
initial
  begin
  $monitor ($time,"A=%b,B=%b,C=%b,Y=%b",A,B,C,Y);
    A=1;B=1;C=1;
    #2 B=0;
    #5 A=1;B=1;C=1;
    #5 $finish;
  end
endmodule

Create a new project and compile the code. Shown below SILOS III simulation result with top portion header deleted, 


Reading "tutdelay.v"
sim to 0
	Highest level modules (that have been auto-instantiated):
		stimulus
	7 total devices.
	Linking ...

	8 nets total: 16 saved and 0 monitored.
	67 registers total: 67 saved.
	Done.                 
                   0A=1,B=1,C=1,Y=1

	0 State changes on observable nets.

	Simulation stopped at the end of time 0.000us.
Ready: sim 
                   2A=1,B=0,C=1,Y=1
                   4A=1,B=0,C=1,Y=0
                   6A=1,B=0,C=1,Y=1
                   7A=1,B=1,C=1,Y=1

	12 State changes on observable nets.

	Simulation stopped at the end of time 0.120us.
Ready:

Click "Data Analyzer",

and perform "drag-and-drop" signals from the Verilog source code to the Data Analyzer window, we have the following result.

2. Static-1 Circuit Hazard

Our illustration show the input signal change from:

ABC = 111 to 101

If all the gates are ideal, this single input value change should not affect the value of the output y = 1. This is the way we learn them from the textbook. But real-life digital gates do possess hard to predict amount of propagation delays. As demonstrated by Verilog a short undesirable negative-going "spike" exist. If the succeeding driven circuit is of fast logic families, this spike can cause malfunctioning in the overall circuit. Our sample circuit is known to possess a Static-1 Hazard.

3. Methods of Eliminating Possible Circuit Hazard:

Method 1: - Use gate "blind" to signal glitches

Use output NAND gate that possess longer propagation delay. If we change the propagation from #1 to #3 
on the last NAND gate, the overall circuit is blind to "glitches".

Simulation Result:

Method 2: - Add Redundant K-covering to Avoid input transition from one K-map covering to another disjoin K-map covering.

	Original: Y = A B + /B C	Modified: Y = A B + /B C + A C 
               

The Code:

//TUTdelay2.v
//Demonstrate delay in circuit: y = a b + /b c + a c

`timescale 10ns/1ns

module DELAY(y,a,b,c);
  input a,b,c;
  output y;
  wire w1,w2,w3,w4;
  not #2(w1,b);
  nand #1(w2,w1,c);
  nand #1(w3,a,b);
  nand #1(w4,a,c);
  nand #1(y,w2,w3,w4);
endmodule

//The "Testbench" for DELAY
module tester;
  reg A,B,C;  //Hold input values
  wire Y;     //This is a driven output value

//G1 is a circuit "Instantiation"
  DELAY G1(Y,A,B,C);
initial
  begin
  $monitor ($time,"A=%b,B=%b,C=%b,Y=%b",A,B,C,Y);
    A=1;B=1;C=1;
    #2 B=0;
    #5 A=1;B=1;C=1;
    #5 $finish;
  end
endmodule

Simulation Result,

4. Dynamic Hazards:

A circuit that create two or more output transitions instead of just one transition due to a single input transition is said to possess Dynamic Hazard. The circuit below as shown by the accompanying Verilog code illustrate dynamic hazard. 

	


The Code:






Simulation Result,