Modeling CMOS logic gates: NAND & NOR

(Uses Verilog): module-endmodule, input, output, supply1, supply0, pmos, nmos, reg, wire, initial, begin-end, $monitor, $time, %b, #, $finish $finish, %b

(REF): Introduction to VLSI Circuits and Systems, by J.P. Uyemura, John Wiley & Sons, Inc, 2002 Chapter 10.

CMOS logic gates for NAND and NOR:

Using Verilog nmos & pmos switch-level primitives, a 2-input NAND and 2-input NOR can easily be constructed by the following wiring,

Recall the primitives syntax as follows,

	
	The Verilog Usage Syntax for the primitives are:

	nmos NNAME (out, data, control);
	pmos PNAME (out, data, control);

Verilog Model for 2-input CMOS NAND gate,

//TUTnand2.v
module nand2(out,ina,inb);
  input ina,inb;
  output out;
  wire wn;	//connect the series nmos switches
  supply1 vdd;
  supply0 gnd;
  pmos p1(out,vdd,ina);
  pmos p2(out,vdd,inb);
  nmos n1(wn,gnd,ina);
  nmos n2(out,wn,inb);
endmodule

//Testbench for nand2
module tester;
  reg INA,INB;      //Hold inputs 
  wire WN,OUT;      //Driven signal values

//G1 is an Instantiation of nand2
  nand2 G1(OUT,INA,INB);
initial
  begin
  $monitor ($time,"INA=%b,INB=%b,OUT=%b",INA,INB,OUT);
    INA=0;INB=0;
    #2 INB=1;
    #1 INA=1;INB=0;
    #1 INB=1;
    #2 $finish;
  end
endmodule

Likewise the Verilog keywords: supply1 and supply0 representing the power supply is required in the above code.

Create a new project and compile the code. Shown below SILOS III simulation result with top portion header deleted,


Reading "tutnand2.v"
sim to 0
	Highest level modules (that have been auto-instantiated):
		tester
	7 total devices.
	Linking ...

	7 nets total: 15 saved and 0 monitored.
	66 registers total: 66 saved.
	Done.                 
                   0INA=0,INB=0,OUT=1

	0 State changes on observable nets.

	Simulation stopped at the end of time 0.
Ready: sim 
                   2INA=0,INB=1,OUT=1
                   3INA=1,INB=0,OUT=1
                   4INA=1,INB=1,OUT=0

	17 State changes on observable nets.

	Simulation stopped at the end of time 6.
Ready:

Simulation Waveform,

Verilog Model for 2-input CMOS NOR gate,

//TUTnor2.v
module nor2(out,ina,inb);
  input ina,inb;
  output out;
  wire wn;	//connect the series nmos switches
  supply1 vdd;
  supply0 gnd;
  pmos p1(wp,vdd,ina);
  pmos p2(out,wp,inb);
  nmos n1(out,gnd,ina);
  nmos n2(out,gnd,inb);
endmodule

//Testbench for nor2
module tester;
  reg INA,INB;      //Hold inputs 
  wire WN,OUT;      //Driven signal values

//G1 is an Instantiation of nand2
  nor2 G1(OUT,INA,INB);
initial
  begin
  $monitor ($time,"INA=%b,INB=%b,OUT=%b",INA,INB,OUT);
    INA=0;INB=0;
    #2 INB=1;
    #1 INA=1;INB=0;
    #1 INB=1;
    #2 $finish;
  end
endmodule
/pre>

Likewise the Verilog keywords: supply1 and supply0 representing the power supply is required in the above code.

Create a new project and compile the code. Shown below SILOS III simulation result with top portion header deleted,


Reading "tutnor2.v"
sim to 0
	Highest level modules (that have been auto-instantiated):
		tester
	7 total devices.
	Linking ...

	7 nets total: 15 saved and 0 monitored.
	66 registers total: 66 saved.
	Done.                 
                   0INA=0,INB=0,OUT=1

	0 State changes on observable nets.

	Simulation stopped at the end of time 0.
Ready: sim 
                   2INA=0,INB=1,OUT=0
                   3INA=1,INB=0,OUT=0
                   4INA=1,INB=1,OUT=0

	19 State changes on observable nets.

	Simulation stopped at the end of time 6.
Ready:

Simulation Waveform,