CMOS Digital Switches are Built-In Primitives in Verilog

(Uses Verilog): module-endmodule, input, output, supply1, supply0, pmos, nmos, reg, wire, initial, begin-end, $monitor, $time, %b, #, $finish $finish, %b

(REF): Introduction to VLSI Circuits and Systems, by J.P. Uyemura, John Wiley & Sons, Inc, 2002 Chapter 10.

nmos and pmos Switch-Level Primitives:

CMOS digital IC modeling are easily perform in Verilog, because the language has built-in CMOS switch-level primitves:

	
	The Verilog Usage Syntax for the primitives are:

	nmos NNAME (out, data, control);
	pmos PNAME (out, data, control);

Modeling "CMOS Inverter" Using the nmos and pmos Switch Primitives:

Verilog Model for CMOS Inverter,

//TUTcmos_inv.v
module cmos_inv(out,in);
  input in;
  output out;
  supply1 vdd;
  supply0 gnd;
  pmos p1(out,vdd,in);
  nmos n1(out,gnd,in);
endmodule

//Testbench for cmos_inv
module tester;
  reg IN;      //Hold input 
  wire OUT;    //Driven Output value

//G1 is an Instantiation of cmos_inv
  cmos_inv G1(OUT,IN);
initial
  begin
  $monitor ($time,"IN=%b,OUT=%b",IN,OUT);
    IN=0;
    #2 IN=1;
    #5 IN=0;
    #5 $finish;
  end
endmodule

Above code uses the following two Verilog keywords:

supply1 - defines the power supply vdd,
supply0 - defines the power supply ground.

Create a new project and compile the code. Shown below SILOS III simulation result with top portion header deleted,



Reading "tutcmos_inv.v"
sim to 0
	Highest level modules (that have been auto-instantiated):
		tester
	5 total devices.
	Linking ...

	5 nets total: 13 saved and 0 monitored.
	65 registers total: 65 saved.
	Done.                 
                   0IN=0,OUT=1

	0 State changes on observable nets.

	Simulation stopped at the end of time 0.
Ready: sim 
                   2IN=1,OUT=0
                   7IN=0,OUT=1

	10 State changes on observable nets.

	Simulation stopped at the end of time 12.
Ready:

Simulation Waveform,